Wafer level packaging has been proposed to stack wafers together to produce extremely dense electronic packages. Through silicon via (TSV) process is one of the techniques used in wafer level packaging. It enables the production of small form factor devices and stacking of wafers to provide integration. Although TSV may provide higher reliability and less parasitic effect, it, however, has a high coefficient of thermal expansion (CTE) than the wafer substrate such as silicon. The CTE mismatch may result in significant stress in the substrate and the TSV. As such, TSV produces high stress which may impact yield and is also a relatively expensive technique. This reduces throughput and leads to an increase in the manufacturing cost of the devices.
It is desirable to provide packages with increased density, high reliability and low manufacturing cost.